(i) Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, particularly to a non-volatile semiconductor memory device which can electrically be rewritten.
(ii) Description of the Related Art
Recently, with the greatly increased prevalence of cellular phones, digital still cameras or other small-size information apparatus, there has been an increasing demand for ferro-electric random access memory, EPROM (Erasable and Programmable Read Only Memory), EEPROM (Electrical Erasable and Programmable Read Only Memory), flash memory or other non-volatile semiconductor memories that can electrically be rewritten. EEPROM, especially, can easily update firmware after products are delivered or repeatedly store photographed images. Flash memory, also termed flash EEPROM, is capable of performing data erasures in all memory storage areas or in selected block storage areas. The flash memory of which each memory cell is constituted of one transistor has an advantage that it can be more easily highly integrated than EEPROM.
FIG. 4 shows an example of a prior art cell transistor 30 constituting a memory cell of a flash memory. The cell transistor 30 is termed a stacked gate type, in which two gate electrodes GP, i.e., a floating gate FG, and a control gate CG are alternately stacked.
When data is written into the cell transistor 30, for example, as shown in FIG. 5A, an electric potential of 5 V is applied to a source S of the cell transistor 30 selected via a bit line BL, while an electric potential of 12 V is applied to the control gate CG via a word line WL. In this condition, the electric potential of the floating gate FG is increased, and hot electrons generated in the vicinity of the source S are supplied to the floating gate FG. Additionally, the bit line BL and the word line WL not connected to the selected cell transistor 30, and the drains D of the cell transistors 30 are set to 0 V via the common drain line DL.
When the electrons are supplied to the floating gate FG, the floating gate FG is negatively charged. Therefore, a channel CH formed between the source S and the drain D is turned off.
When the data is erased from the cell transistors 30, as shown in FIG. 5B, the control gates CG of all cell transistors 30 are set to 0 V via the word lines WL. Additionally, all bit lines BL, i.e., the sources S of all cell transistors 30 are opened. Moreover, an electric potential of 15 V is applied to the drain of each cell transistor 30 via the common drain line DL. In this condition, the electrons in the floating gate FG are extracted toward the drain D by a FN (Fowler-Nordheim) tunnel current. The erasing operation is performed for all cell transistors 30 or for the cell transistors 30 in the selected block.
When the electrons of the floating gate FG are extracted, the floating gate FG is charged positive. Therefore, the channel CH formed between the source S and the drain D is placed in a condition in which it can be turned on, i.e., it is turned on when selected.
When data is read from the cell transistor 30, as shown in FIG. 5C, an electric potential of 2.5 V is applied to the source S of the cell transistor 30 selected via the bit line BL, an electric potential of 5 V is applied to the control gate CG via the word line WL, and an electric potential of 0 V is applied to the drain D via the common drain line DL.
During reading, the electric current flowing between the source S and the drain D of the cell transistor 30 varies in magnitude in accordance with whether the channel CH of the cell transistor 30 is turned on or off. Specifically, in the erasing condition in which the channel CH is on, the electric current more easily flows between the source S and the drain D than the writing condition in which the channel CH is off. Therefore, if the difference of the electric current is detected by a sense amplifier connected to the bit line BL, the value of the data stored in the memory cell can be read.
In an actual memory chip having multiple cell transistors 30, subtle variation may be generated in the erasing/writing characteristics of the cell transistors 30. As a result, for example, even when the same electric potential is applied to the cell transistors 30 to erase the data therefrom, the electric potential necessary for the erasing is reached in some cell transistors 30, but the necessary electric potential may not be reached in other cell transistors 30.
In this case, if the electric potential of the cell transistor 30 in which erasing can easily be performed is raised in accordance with the cell transistor 30 in which erasing cannot be easily performed, the electrons are excessively extracted from the floating gate FG of the cell transistor 30 in which erasing is easily performed, and the channel CH is constantly turned on. This causes a problem that a reading error is generated by the electric current of the cell transistor 30 which is not selected at the time of reading. The problem of so-called excessive erasing is caused.
To solve the problem, following methods have been heretofore performed:
(1) When data is written, the time for supplying electrons to the floating gate FG is adjusted to control the amount of electric charges of the floating gate FG, so that the electrons are prevented from being excessively supplied to that floating gate FG. Moreover, when data is erased, the time for extracting the electrons from the floating gate FG is adjusted to control the amount of electric charges of the floating gate FG, so that the electrons are prevented from being excessively extracted from the floating gate FG.
(2) At the time of writing data, after writing is performed for the predetermined time, a verification reading is performed to confirm whether or not excess electrons are supplied to the floating gate FG. By repeating the writing and the verification reading, the amount of electric charges of the floating gate FG is controlled. Moreover, at the time of erasing data, after erasing is performed for the predetermined time, verification reading is performed to confirm whether or not excess electrons are extracted from the floating gate FG. By repeating the erasing and the verification reading, the amount of electric charges of the floating gate FG is controlled.
(3) At the time of writing data, after writing is performed, verification reading is performed. Subsequently, after the electric potentials of the word line WL and the bit line BL are slightly raised, writing is performed again. Thereafter, a verification reading is performed. By repeating the writing and the verification reading, the electric potentials of the word line WL and the bit line BL are gradually raised to perform writing, so that the amount of electric charges of the floating gate FG is controlled. At the time of erasing data, after erasing is performed, a verification reading is performed. Subsequently, after the electric potential of the common drain line DL is slightly raised, erasing is performed again. Thereafter, a verification reading is performed. By repeating the erasing and the verification reading, the electric potential of the common drain line DL is gradually raised to perform erasing, so that the amount of electric charges of the floating gate FG is controlled.
(4) Before erasing data, data is written to the cell transistor 30 in which data is not yet written. After all cell transistors 30 are placed in the writing condition, an erasure is performed.
Since the above controls (1) to (4) are complicated, there is a problem that control circuit structures are complicated. Another problem is that the operation speed of the memory is lowered to perform the complicated control.
Recently, in order to enhance the integration degree of the flash memory, there has been proposed a multilevel memory in which three or more values are stored, instead of storing two values (one bit), i.e., the erasing and writing conditions in each memory cell.
Even in the multilevel memory, the excess erasing needs to be prevented. For the purpose, the threshold voltage of the cell transistor 30 needs to be controlled in a range of voltages in which excess erasing is not performed. Since the narrow voltage range needs to be divided into plural sections to correspond to each data value, it is disadvantageously difficult to control the threshold voltage.